1. Field of the Invention
The present invention generally relates to the art of semiconductor memories, and more specifically to a flash or block erase electrically erasable programmable read-only memory (EEPROM) cell and array with bifurcated floating gates.
2. Description of the Related Art
A flash or block erase EEPROM semiconductor memory includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting select transistors which would enable the cells to be erased independently. All of the cells are erased together as a block.
A conventional flash EEPROM is described in an article entitled "A FLASH-ERASE EEPROM CELL WITH AN ASYMMETRIC SOURCE AND DRAIN STRUCTURE", by H. Kume et al, IEDM, 25.8, 1987, pp. 560-563. Each cell includes a source and a drain which are formed on opposite sides of a channel region in a substrate. A thin tunnel oxide layer, a floating gate, a thick gate oxide layer and a control gate are formed over the channel region.
The cell is programmed by applying, typically, 12 V to the control gate, 6 V to the drain and grounding the source, which causes hot electrons to be injected from the drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein which increases the threshold voltage of the cell to a value in excess of approximately 6 V.
The cell is read by applying 5 V to the control gate and 1 V to the drain, and sensing the impedance of the cell at the source. If the cell is programmed and the threshold voltage (6 V) is higher than the control gate voltage (5 V), the control gate voltage will be insufficient to enhance the channel and the cell will appear as a high impedance. If the cell is not programmed or erased, the threshold voltage will be low, the control gate voltage will enhance the channel and the cell will appear as a low impedance.
The cell is erased by applying typically 12 V to the source, grounding the control gate and allowing the drain to float. This causes the electrons which were injected into the floating gate during programming to be removed by Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source.
A problem with the conventional flash EEPROM cell configuration is that due to manufacturing tolerances, some cells become over-erased before other cells become erased sufficiently. The floating gates of the over-erased cells are depleted of electrons and become positively charged. This causes the over-erased cells to function as depletion mode transistors which cannot be turned off by normal operating voltages applied to their control gates, and introduces leakage during subsequent program and read operations.
A known method of preventing over-erasure is to provide an adaptive erasing algorithm in which the erasing voltages are applied to the control gates as a series of pulses of varying period. This method is complicated and requires additional circuitry for generating the erase pulses in accordance with the algorithm.
The effects of over-erasure can be compensated for by means of a split-gate (also known as stacked- or pass-gate) configuration in which a section of the control gate is disposed in series between the source and the floating gate. The region of the channel which underlies the series section of the control gate can be turned off by the control gate voltage, thereby providing the cell with a stable threshold voltage after erasure and minimizing leakage. A typical split-gate EEPROM is described in an article entitled "A 128 K Flash EEPROM Using Double-Polysilicon Technology", by G. Samacisa et al, IEEE J. Solid-State Circuits, Vol. SC-22, No. 5, Oct. 1987, pp. 676-683.
Although achieving stable erasure without the necessity of utilizing an adaptive algorithm, a split-gate EEPROM requires higher applied voltages to achieve erasure than the basic EEPROM. This is because the floating gate is spaced from the source by the series section of the control gate and the intervening gate oxide layer. A higher potential difference is required to accomplish erasure by Fowler-Nordheim tunneling through the thick gate oxide layer of the split-gate EEPROM than through the thin tunnel oxide layer of the basic EEPROM.